![]() | Name | Last modified | Size | Description |
---|---|---|---|---|
![]() | Parent Directory | - | ||
![]() | lane1_t30-DMSO-AhR-ChIP.bw | 2016-07-18 17:33 | 507M | |
![]() | lane1_t30-TCDD-AhR-ChIP.bw | 2016-07-18 18:12 | 503M | |
![]() | tcdd_t2A.bw | 2017-05-19 19:20 | 489M | |
![]() | tcdd_t24B.bw | 2017-05-19 19:16 | 482M | |
![]() | t90-TCDD-AhR-ChIP.bw | 2016-11-29 13:54 | 449M | |
![]() | lane1_t30-Coaltar-AhR-ChIP.bw | 2016-07-18 16:47 | 431M | |
![]() | coaltar_t24A.bw | 2017-05-19 18:51 | 424M | |
![]() | control_t0B.bw | 2017-05-19 19:05 | 419M | |
![]() | t90-control-AhR-ChIP.bw | 2016-11-29 13:49 | 397M | |
![]() | tcdd_t24A.bw | 2017-05-19 19:13 | 395M | |
![]() | control_t0A.bw | 2017-05-19 19:02 | 389M | |
![]() | coaltar_t2B.bw | 2017-05-19 18:59 | 362M | |
![]() | lane1_t0-AhR-ChIP-input.bw | 2016-07-18 15:22 | 360M | |
![]() | coaltar_t24B.bw | 2017-05-19 18:54 | 357M | |
![]() | lane1_t0-control-AhR-ChIP.bw | 2016-07-18 16:05 | 351M | |
![]() | tcdd_t2B.bw | 2017-05-19 19:23 | 337M | |
![]() | TCDD_AHR_Rep_1.bw | 2018-01-15 13:13 | 335M | |
![]() | coaltar_t2A.bw | 2017-05-19 18:56 | 333M | |
![]() | TCDD_AHR_Rep_4.bw | 2018-01-15 14:20 | 325M | |
![]() | DMSO_AHR_Rep_1.bw | 2018-01-15 11:32 | 313M | |
![]() | TCDD_AHR_Rep_2.bw | 2018-01-15 13:46 | 310M | |
![]() | t0-control-H3K27ac-ChIP.bw | 2018-01-26 18:20 | 308M | |
![]() | t30-TCDD-H3K27ac-ChIP.bw | 2018-01-26 18:41 | 296M | |
![]() | control_t24B.bw | 2017-05-19 19:10 | 289M | |
![]() | control_t24A.bw | 2017-05-19 19:07 | 278M | |
![]() | t90-TCDD-H3K27ac-ChIP.bw | 2018-01-26 19:09 | 275M | |
![]() | DMSO_AHR_Rep_2.bw | 2018-01-15 12:05 | 259M | |
![]() | t90-Coaltar-AhR-ChIP.bw | 2016-11-30 16:34 | 230M | |
![]() | DMSO_AHR_Rep_4.bw | 2018-01-15 12:35 | 204M | |